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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3729
5000 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
The PD3729 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3729 has 3 rows of 5000 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and even pixels. Therefore, it is suitable for 400 dpi/A3 high-speed color digital copiers and so on.
FEATURES
* Valid photocell * Line spacing * Color filter * Resolution * Data rate * Output type * Power supply * On-chip circuits : 5000 pixels x 3 : 40 m (4 lines) Red line-Green line, Green line-Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx*hour) : 16 dot/mm (400 dpi) A3 (297 x 420 mm) size (shorter side) : 30 MHz MAX. (15 MHz/1 output) : 2 outputs in phase/color : +12 V : Reset feed-through level clamp circuits Voltage amplifiers
* Photocell's pitch : 10 m
* Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number Package CCD linear image sensor 24-pin ceramic DIP (400 mil)
PD3729D
The information in this document is subject to change without notice. Document No. S12883EJ1V0DS00(1st edition) Date published November 1998 N CP(K) Printed in Japan
(c)
1998
PD3729
BLOCK DIAGRAM
CLB
20
1L
19
VOD 5
GND GND GND 4 12 21
1
15
2
16
VOUT2 (Blue, even)
22
D128
CCD analog shift register Transfer gate
S4999 S5000 D129 D27
.....
S1 S2
Photocell (Blue)
.....
D134
14
TG1 (Blue)
VOUT1 (Blue, odd)
23
Transfer gate CCD analog shift register
VOUT3 24 (Green, odd)
D128 D27
CCD analog shift register Transfer gate
S4999 S5000 D129 S1 S2
.....
Photocell (Green)
.....
D134
13
TG2 (Green)
VOUT4 1 (Green, even)
Transfer gate CCD analog shift register
VOUT6 (Red, even)
2
D128
CCD analog shift register Transfer gate
S4999 S5000 D129 D27 S1 S2
.....
Photocell (Red)
.....
D134
11
TG3 (Red)
VOUT5 (Red, odd)
3
Transfer gate CCD analog shift register
6
9
10
RB
1
2
2
PD3729
PIN CONFIGURATION (Top View) CCD linear image sensor 24-pin ceramic DIP (400 mil)
* PD3729D
Output signal 4 (Green, even)
VOUT4
1
24
VOUT3 Output signal 3 (Green, odd)
Output signal 6 (Red, even)
VOUT6
2
23
VOUT1 Output signal 1 (Blue, odd)
1
1
1
Output signal 5 (Red, odd)
VOUT5
3
22
VOUT2 Output signal 2 (Blue, even)
Ground
GND
4
21
GND
Ground
Output drain voltage
VOD
5
20
CLB Reset feed-through level clamp clock 1L
Last stage shift register clock 1
Reset gate clock
RB
6
19
Green
No connection
NC
7
Blue
Red
18
NC
No connection
No connection
NC
8
17
NC
No connection
Shift register clock 1
1
9
16
2
Shift register clock 2
Shift register clock 2
2
10
15
1
Shift register clock 1
5000
5000
5000
Transfer gate clock 3 (for Red) TG3
11
14
TG1 Transfer gate clock 1 (for Blue)
Ground
GND
12
13
TG2 Transfer gate clock 2 (for Green)
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
10 m Blue photocell array 4 lines (40 m) 10 m Green photocell array 4 lines (40 m) 10 m Red photocell array
7 m
3 m
10 m
Channel stopper
Aluminum shield
3
PD3729
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature VOD V1, V1L, V2 VRB VCLB VTG1 to VTG3 TA Tstg Symbol Ratings -0.3 to +15 -0.3 to +15 -0.3 to +15 -0.3 to +15 -0.3 to +15 -25 to +70 -40 to +100 Unit V V V V V C C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level Transfer gate clock low level Data rate VOD V1H, V1LH, V2H V1L, V1LL, V2L VRBH VRBL VCLBH VCLBL VTG1H to VTG3H VTG1L to VTG3L 2fRB Symbol MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 -0.3 - TYP. 12.0 5.0 0 5.0 0 5.0 0 V1HNote 0 2 MAX. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 V1HNote +0.5 30 Unit V V V V V V V V V MHz
Note
When Transfer gate clock high level (VTG1H to VTG3H) is higher than Shift register clock high level (V1H), Image lag can increase.
4
PD3729
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 12 V, fRB = 1 MHz, data rate = 2 MHz, storage time = 10 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal
Note 1
Symbol Vsat SER SEG SEB PRNU ADS1 ADS2
Test Conditions
MIN. 1.5
TYP. 2.0 0.32 0.37 0.29
MAX. -
Unit V lx*s lx*s lx*s
VOUT = 1 V Light shielding
6 1.0 0.5
18 5.0 5.0 5.0 5.0 700 0.5 8.1 7.0 8.9 5.0 5.0 6.0
% mV mV mV mV mW k V/lx*s V/lx*s V/lx*s % % V ns
Dark signal non-uniformity
Note 1
DSNU1 DSNU2
Light shielding
2.0 1.0 500 0.3 4.3 3.8 4.7 6.2 5.4 6.8 2.0 1.0 4.0 5.0 25 0 95 98
Power consumption Output impedance Response Red Green Blue Image lag
Note 1
PW ZO RR RG RB IL1 IL2 VOUT = 1 V
Offset level
Note 2 Note 3
VOS td RI TTE VOUT = 1 V VOUT = 1 V VOUT = 1 V, data rate = 30 MHz
Output fall delay time Register imbalance
4.0
% %
Total transfer efficiency
Response peak
Red Green Blue
630 540 460 DR11 DR12 DR21 DR22 Vsat /DSNU1 Vsat/DSNU2 Vsat /1 Vsat/2 Light shielding Light shielding -500 - - 1000 2000 2000 4000 +200 1.0 0.5 +500 - -
nm nm nm times times times times mV mV mV
Dynamic range
Note 1
Reset feed-through noise Random noise
Note 1
Note 2
RFTN 1 2
Notes 1. ADS1, DSNU1, IL1, DR11 and DR21 show the specification of VOUT1 and VOUT2. ADS2, DSNU2, IL2, DR12 and DR22 show the specification of VOUT3 to VOUT6. 2. Refer to TIMING CHART 2. 3. When the fall time of 1L (t2') is the TYP. value (refer to TIMING CHART 2).
5
PD3729
INPUT PIN CAPACITANCE (TA = +25 C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol Pin name Pin No. C1 MIN. TYP. 500 500 500 500 50 50 50 70 70 70 MAX. 800 800 800 800 Unit pF pF pF pF pF pF pF pF pF pF
1
9 15
Shift register clock pin capacitance 2
C2
2
10 16
Last stage shift register clock pin capacitance Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance
CL CRB CCLB CTG
1L RB CLB TG1 TG2 TG3
19 6 20 14 13 11
Remark Pins 9 and 15 (1), 10 and 16 (2) are each connected inside of the device.
6
TIMING CHART 1 (for each color)
TG1 to TG3
1
2 1L
RB
CLB
Note Note
5125 5127 5129
5131 5133 5135 5132 5134 5136
VOUT1, 3, 5
5126 5128 5130
VOUT2, 4, 6
Optical black (96 pixels) Invalid photocell (6 pixels)
Valid photocell (5000 pixels) Invalid photocell (6 pixels)
5138
120 122 124 126 128 130 132
10 12 14 16 18 20 22 24 26 28 30
2 4 6
8
5137
119 121 123 125 127 129 131
9 11 13 15 17 19 21 23 25 27 29
1 3 5
7
PD3729
Note
Input the RB and CLB pulses continuously during this period, too.
7
PD3729
TIMING CHART 2 (for each color)
t1
t2
1
10 %
90 %
2
90 % 10 % 90 % 10 % t1' 90 % 10 % t5 t3 t10 t8 90 % 10 % td t7 t9 t11 t6 t4 t2'
1L
RB
CLB
VOUT1 to VOUT6
RFTN
VOS 10 %
TG1 to TG3, 1, 2 TIMING CHART
t13 90 % t12 t14
TG1 to TG3
10 % t15 t16
90 %
1
2
8
PD3729
Symbol t1, t2 t1', t2' t3 t4 t5, t6 t7 t8, t9 t10 t11 t12 t13, t14 t15, t16
MIN. 0 0 20 20 0 20 0 -10Note 1 -5Note 2 5000 0 900
TYP. 50 5 50 100 20 150 20 +50 +50 10000 50 1000
MAX.
Unit ns ns ns
-
ns ns ns ns
-
ns ns ns ns ns
Notes 1. MIN. of t10 shows that the RB and CLB overlap each other.
RB
t10
90 %
CLB
90 %
2. MIN. of t11 shows that the 1L and CLB overlap each other.
1L
90 %
CLB
t11
90 %
1, 2 cross points
1
1L, 2 cross points
2
2 V or more
2
2 V or more
1L
2 V or more
0.5 V or more
Remark Adjust cross points (1, 2) and (1L, 2) with input resistance of each pin.
9
PD3729
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
x x 100 x x : maximum of xj - x
5000 j=1
PRNU (%) =
xj
5000
x=
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x x
4.
Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5000 j=1
dj
5000 dj : Dark signal of valid pixel number j
ADS (mV) =
10
PD3729
5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of dj - ADS j = 1 to 5000 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6.
Output impedance: ZO Impedance of the output pins viewed from outside.
7.
Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source (spectral characteristic).
8.
Image lag: IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light
ON
OFF
VOUT V1 VOUT
V1 IL (%) = VOUT
x100
11
PD3729
9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n
2 n RI (%) =
(V2j - 1 - V2j)
j= 1
2
1 n
Vj
j= 1
n
x 100
n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
100
(mV) =
(Vi - V)
i=1
2
, V=
1
100
100
100 i=1
Vi
Vi: A valid pixel output signal among all of the valid pixels for each color
VOUT
V1 V2
line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
...
line 100
...
12
PD3729
STANDARD CHARACTERISTIC CURVES
DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 C)
4 Relative Output Voltage Relative Output Voltage 10 20 30 40 50 1
2
1
0.5
0.25
0.2
0.1 0
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA(C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (TA = +25 C) 100 B
80 R
Response Ratio (%)
60 G
40
20 G B 0 400 500 600 Wavelength (nm) 700 800
13
PD3729
APPLICATION CIRCUIT EXAMPLE
+5 V 10 + 10 F/16 V 0.1 F B4 B6 B5 1 2 3 4 5 VOUT4 VOUT6 VOUT5 GND VOD + +12 V
PD3729
24 23 22 21 20 19 18 17 16 15 14 13 2 2 2 2 47 47
0.1 F 47 F/25 V B3 B1 B2 +
+5 V
VOUT3 VOUT1 VOUT2 GND
0.1 F 10 F/16 V
CLB 1L
NC NC
CLB 1L
RB
47
6 7 8
RB
NC NC
1 2 TG
2 2 2
9 10 11 12
1 2 TG3
GND
2 1 TG1 TG2
Remark The inverters shown in the above application circuit example are the 74AC04.
B1 to B6 EQUIVALENT CIRCUIT
+12 V 47 F/25 V +
0.1 F
4.7 k 110 CCD VOUT 47 2SA1005 1 k 2SC945
14
PD3729
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 24-PIN CERAMIC DIP (400mil)
(Unit : mm)
68.00.4
1
10.60.6 The 1st valid pixel
9.40.7
2
10.030.15
10.16
3
1.270.05
(4.33)
(2.33)
0.460.05 27.94
2.54
3.500.5 0.970.3 3.300.32 2.00.3
4
0.250.05
Name Glass cap 1 The 1st valid pixel 2 The 1st valid pixel 3 The surface of the chip 4 The bottom of the package
Dimensions 67.0 x 8.5 x 1.0
Refractive index 1.5
The edge of the package The center of the pin1 The top of the glass cap (Reference) The surface of the chip
24D-1CCD-PKG1-1
15
PD3729
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device
PD3729D: CCD linear image sensor 24-pin ceramic DIP (400 mil)
Process Partial heating method Conditions Pin temperature: 300 C or below, Heat time: 3 seconds or less (per pin)
16
PD3729
[MEMO]
17
PD3729
[MEMO]
18
PD3729
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee outpin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
19
PD3729
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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